The majority of built-in test mechanisms currently employed for testing digital circuitry (state machines and combinational logic) fall into one of two primary categories:
1--limited detection capability off-line test systems; and PA1 2--single or multiple bit correcting fault tolerant systems. Fault-tolerant systems tend to be extremely complex and are unnecessary for most signal processing applications. On the other hand, limited detection off-line test systems typically require that the circuitry under test interrupt its normal signal processing function, so that it may execute a self-test sequence. In addition to the drawback of halting operation, self-testing generally has a poor or only moderate level of effectiveness, in attempting to substantiate the absence of stuck-at-(one or zero) nodes. Most current test procedures involve either a functional system test in which the system operation of prescribed functions are tested, or the system is tested by a scan-in/scan-out test which uses test vectors to check flip-flops and combinational logic.
Currently, the functional test approach is the most widely employed; however, in general, it also suffers from the lowest degree of test effectiveness for digital logic in detecting all possible `stuck at?` nodes, etc. and requires the highest level of customization and considerable interface isolation and simulation. In addition to problems of controllability and accessibility, there are also ample opportunities for the test circuitry itself to fail, thereby either indicating a false operational failure of the circuit being tested or preventing the reporting of an actual operational failure. Moreover, functional circuit testing requires that the test circuitry be customized to match both the architecture and functions of the circuit under test and often entails as much or greater design effort than the original circuit.
The `scan-in/scan-out` type of test procedure, which is a more recent and popular scheme and has achieved reasonably acceptable levels of circuit and pinout overhead (e.g. twenty to fifty percent gate overhead depending on application and as few as two additional input/output pins per chip), is based upon converting all state machines in a system into a sequence of shift registers and piping long test vectors through the sequence to check for faulty flip-flops, and then loading test vectors into the combinational logic in parallel and shifting the vectors out serially so as to effectively transfer the combinational logic into and out of each flip-flop.
While the scan-in/scan-out scheme is a more general approach to the problem and is usually incorporated into the integrated circuitry containing the state machine and combinational logic, rather than being built around these circuits as functional testers, it still has a number of significant limitations. First of all, the system under test must be interrupted to be tested. Secondly, a custom test vector which matches the user's circuit configuration must be generated. Thirdly, the level of testability that can be achieved by this technique is inherently limited.
Thus, there exists a gap in the technology; i.e. the lack of a satisfactory method of performing a high level of on-line testing without the extreme complexities (three or more times the complexity of the original circuit function) that accompany fault-tolerant systems.